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features provides analog pcm line interface for t1 and e1 applications provides line driver, and data and clock recovery functions transmit side jitter attenuation starting at 6 hz, with > 300 ui of jitter tolerance low power consumption (typically 175 mw) b8zs/hdb3/ami encoders/decoders 14 db of transmitter return loss compatible with sonet, m13 , ccitt g.742, and other asynchronous muxes general description the cs61535a combines the complete analog transmit and receive line interface for t1 or e1 applications in a low power, 28-pin device operating from a +5v supply. the device features a transmitter jitter attenuator mak- ing it ideal for use in asynchronous multiplexor systems with gapped transmit clocks. the cs61535a provides a matched, constant impedance output stage to insure signal quality on mismatched, poorly terminated lines. both ics use a digital delay-locked-loop clock and data recovery circuit which is continuously calibrated from a crystal reference to provide excellent stability and jitter tolerance. applications interfacing network transmission equipment such as sonet multiplexor and m13 to a dsx-1 cross connect. interfacing customer premises equipment to a csu. interfacing to e1 links. ordering information cs61535a-ip1 28 pin plastic dip CS61535A-IL1 28 pin plcc (j-leads) may 96 ds40f2 1 crystal semiconductor corporation p.o. box 17847, austin, tx 78760 (512) 445-7222 fax: (512) 445-7581 signal quality monitor 13 ttip tclk 7 rring rtip 19 20 17 11 18 tring 16 tgnd 14 control driver monitor line receiver line driver 15 pulse shaper 3 2 6 4 rclk 8 aclki 27 lloop (sclk) 26 rloop (cs) 25 24 (int) len0 (sdi) len1 (sdo) len2 28 23 (clke) taos 5 mode ami, b8zs, hdb3 coder tpos [tdata] rpos [rdata] rneg [bpv] tneg [tcode] mtip [rcode] mring [pcs] dpm [ais] los 12 21 rv+ 22 rgnd 1 clock & data recovery xtalin 9 xtalout 10 jitter attenuator loop back tv+ [ ] = pin function in extended hardware mode ( ) = pin function in host mode copyright ? crystal semiconductor corporation 1996 (all rights reserved) cs61535a t1/e1 line interface
absolute maximum ratings parameter symbol min max units dc supply (referenced to rgnd,tgnd=0v) rv+ tv+ - - 6.0 (rv+) + 0.3 v v input voltage, any pin (note 1) v in rgnd-0.3 (rv+) + 0.3 v input current, any pin (note 2) i in -10 10 ma ambient operating temperature t a -40 85 c storage temperature t stg -65 150 c warning:operations at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. notes: 1. excluding rtip, rring, which must stay within -6v to (rv+) + 0.3v. 2. transient currents of up to 100 ma will not cause scr latch-up. also ttip, tring, tv+ and tgnd can withstand a continuous current of 100 ma. recommended operating conditions parameter symbol min typ max units dc supply (note 3) rv+, tv+ 4.75 5.0 5.25 v ambient operating temperature t a -40 25 85 c power consumption (notes 4, 5) p c -290350mw power consumption (notes 4, 6) p c -175-mw notes: 3. tv+ must not exceed rv+ by more than 0.3v. 4. power consumption while driving line load over operating temperature range. includes ic and load. digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pf load. 5. assumes 100% ones density and maximum line length at 5.25v. 6. assumes 50% ones density and 300ft. line length at 5.0v. cs61535a 2 ds40f2
digital characteristics (ta = -40 c to 85 c; tv+, rv+ = 5.0v 5%; gnd = 0v) parameter symbol min typ max units high-level input voltage pins 1-4, 17, 18, 23-28 (notes 7, 8, 9) v ih 2.0 - - v low-level input voltage pins 1-4, 17, 18, 23-28 (notes 7, 8, 9) v il --0.8v high-level output voltage (i out = -40 m a) pins 6-8, 11, 12, 25 (notes 7, 8, 10) v oh 4.0 - - v low-level output voltage (i out = 1.6 ma) pins 6-8, 11, 12, 23, 25 (notes 7, 8, 10) v ol --0.4v input leakage current (except pin 5) - - 10 m a low-level input voltage, pin 5 v il --0.2v high-level input voltage, pin 5 v ih (rv+) - 0.2 - - v mid-level input voltage, pin 5 (note 11) v im 2.3 - 2.7 v notes: 7. this specification guarantees ttl compatibility (v oh = 2.4v @ i out = -40 m a). 8. in host mode, pin 23 is an open drain output and pin 25 is a tristate output. 9. pins 17 and 18 of the cs61535a are digital inputs in the extended hardware mode. 10. output drivers will drive cmos logic levels into a cmos load. 11. as an alternative to supplying a 2.3-to-2.7v input, this pin may be left floating. analog specifications (ta = -40 c to 85 c; tv+, rv+ = 5.0v 5%; gnd = 0v) parameter min typ max units jitter attenuator jitter attenuation curve corner frequency (note 12) - 6 - hz t1 jitter attenuation in remote loopback (note 13) jitter freq. [hz] amplitude [uipp] 10 10 100 10 500 10 1k 5 10k, 40k 0.3 3.0 20 35 40 40 6.0 30 35 50 50 - - - - - db db db db db e1 jitter attenuation in remote loopback (note 14) jitter freq. [hz] amplitude [uipp] 10 1.5 100 1.5 400 1.5 1k 1.5 10k, 100k 0.2 3.0 20 30 35 35 6.0 32 43 50 50 - - - - - db db db db db attenuator input jitter tolerance (note 15) 12 23 - ui notes: 12. not production tested. parameters guaranteed by design and characterization. 13. attenuation measured at the demodulator output of an hp3785b with input jitter equal to 3/4 of measured jitter tolerance using a measurement bandwidth of 1 hz (10 1khz) centered around the jitter frequency. with a 2 15 -1 prbs data pattern. crystal must meet specifcations in cxt6176/8192 datasheet. 14. jitter measured at the demodulator output of an hp3785a using a measurement bandwidth not to exceed 20 hz centered around the jitter frequency. with a 2 15 -1 prbs data pattern. crystal must meet specifications in cxt6176/8192 datasheet. 15. output jitter increases significantly when attenuator input jitter tolerance is exceeded. cs61535a ds40f2 3
analog specifications (ta = -40 c to 85 c; tv+, rv+ = 5.0v 5%; gnd = 0v) parameter min typ max units transmitter ami output pulse amplitudes (note 16) e1, 75 w (note 17) e1, 120 w (note 18) t1, fcc part 68 (note 19) t1, dsx-1 (note 20) 2.14 2.7 2.7 2.4 2.37 3.0 3.0 3.0 2.6 3.3 3.3 3.6 v v v v e1 zero (space) level (len2/1/0 = 0/0/0) 75 w application (note 17) 120 w application (note 18) -0.237 -0.3 - - 0.237 0.3 v v recommended output load at ttip and tring - 75 - w jitter added during remote loopback (note 21) 10hz - 8khz 8khz - 40khz 10hz - 40khz broad band - - - - 0.005 0.008 0.010 0.015 0.02 0.025 0.025 0.05 ui ui ui ui power in 2khz band about 772khz (notes 12, 16) 12.6 15 17.9 dbm power in 2khz band about 1.544mhz (notes 12, 16) (referenced to power in 2khz band at 772khz) -29 -38 - db positive to negative pulse imbalance (notes 12, 16) t1, dsx-1 e1 amplitude at center of pulse e1 pulse width at 50% of nominal amplitude - -5 -5 0.2 - - 0.5 5 5 db % % transmitter return loss (notes 12, 16, 22) 51 khz to 102 khz 102 khz to 2.048 mhz 2.048 mhz to 3.072 mhz 8 14 10 - - - - - - db db db transmitter short circuit current (notes 12, 23) - - 50 ma rms notes: 16. using a 0.47 m f capacitor in series with the primary of a transformer recommended in the applications section. 17. amplitude measured at the transformer (cs61535a-1:1 or 1:1.26) output across a 75 w load for line length setting len2/1/0 = 0/0/0. 18. amplitude measured at the transformer (cs61535a-1:1.26) output across a 120 w load for line length setting len2/1/0 = 0/0/0. 19. amplitude measured at the transformer (cs61535a-1:1.15) output across a 100 w load for line length setting len2/1/0 = 0/1/0. 20. amplitude measured across a 100 w load at the dsx-1 cross-connect for line length settings len2/1/0 = 0/1/1, 1/0/0, 1/0/1, 1/1/0 and 1/1/1 after the length of #22 awg abam equivalent cable specified in table 3. the cs61535a requires a 1:1.15 transformer. 21. input signal to rtip/rring is jitter free. values will reduce slightly if jitter free clock is input to tclk. 22. return loss = 20 log 10 abs((z 1 +z 0 )/(z 1 -z 0 )) where z 1 = impedance of the transmitter, and z 0 = impedance of line load. measured with a repeating 1010 data pattern with len2/1/0 = 0/0/0 and a 1:1 transformer terminated with a 75 w load, or a 1:1.26 transformer terminated with a 120 w load. 23. measured broadband through a 0.5 w resistor across the secondary of a 1:1.26 transformer during the transmission of an all ones data pattern for len2/1/0 = 0/0/0. cs61535a 4 ds40f2
analog specifications (ta = -40 c to 85 c; tv+, rv+ = 5.0v 5%; gnd = 0v) parameter min typ max units driver performance monitor mtip/mring sensitivity: differential voltage required for detection -0.60- v receiver rtip/rring input impedance - 50k - w sensitivity below dsx (0db = 2.4v) -13.6 - - db data decision threshold t1, dsx-1 (note 24) t1, dsx-1 (note 25) t1, fcc part 68 and e1 (note 26) 60 53 45 65 65 50 70 77 55 % of peak % of peak % of peak data decision threshold t1 e1 - - 65 50 - - % of peak % of peak allowable consecutive zeros before los 160 175 190 bits receiver input jitter tolerance (note 27) 10khz - 100khz 2khz 10hz and below 0.4 6.0 300 - - - - - - ui ui ui loss of signal threshold (note 28) 0.25 0.30 0.50 v notes: 24. for input amplitude of 1.2 v pk to 4.14 v pk . 25. for input amplitude of 0.5 v pk to 1.2 v pk and from 4.14 v pk to rv+. 26. for input amplitude of 1.05 v pk to 3.3 v pk . 27. jitter tolerance increases at lower frequencies. see figure 11. 28. los goes high after 160 to 190 consecutive zeros are received. a zero is output on rpos and rneg (or rdata) for each bit period where the input signal amplitude remains below the data decision threshold. the analog input squelch circuit operates when the input signal amplitude above ground on the rtip and rring pins falls within the squelch range long enough for the internal slicing threshold to decay within this range. operation of the squelch causes zeros to be output on rpos and rneg as long as the input amplitude remains below 0.25v. during receive los, pulses greater than 0.25v in amplitude may be output on rpos and rneg. los returns low after the ones density reaches 12.5% (based upon 175 bit periods starting with a one and containing less than 100 consecutive zeros) as prescribed in ansi t1.231-1993. cs61535a ds40f2 5
t1 switching characteristics (ta = -40 c to 85 c; tv+, rv+ = 5.0v 5%; gnd = 0v; inputs: logic 0 = 0v, logic 1 = rv+; see figures 1, 2, & 3) parameter symbol min typ max units crystal frequency (note 29) f c - 6.176000 - mhz aclki duty cycle t pwh3 /t pw3 40 - 60 % aclki frequency (note 30) f aclki -1.544-mhz rclk duty cycle (notes 31, 32) t pwh1 /t pw1 - - 78 29 - - % % rclk cycle width (note 32) t pw1 t pwh1 t pwl1 320 130 100 648 190 458 980 240 850 ns ns ns rise time, all digital outputs (note 33) t r - - 85 ns fall time, all digital outputs (note 33) t f - - 85 ns tpos/tneg (tdata) to tclk falling setup time t su2 25 - - ns tclk falling to tpos/tneg (tdata) hold time t h2 25 - - ns rpos/rneg valid before rclk falling (note 34) t su1 150 274 - ns rdata valid before rclk falling (note 35) t su1 150 274 - ns rpos/rneg valid before rclk rising (note 31) t su1 150 274 - ns rpos/rneg valid after rclk falling (note 34) t h1 150 274 - ns rdata valid after rclk falling (note 35) t h1 150 274 - ns rpos/rneg valid after rclk rising (note 31) t h1 150 274 - ns tclk frequency f tclk -1.544-mhz tclk pulse width (notes 12, 31, 34, 36, 37) (notes 35, 36, 37) t pwh2 80 150 - - 500 500 ns ns notes: 29. crystal must meet specifications described in cxt6176/cxt8192 data sheet. 30. aclki provided by an external source or tclk, but not rclk. 31. hardware mode, or host mode (clke = 0). 32. rclk cycle width will vary with extent by which pulses displaced by jitter. specified under worst case jitter conditions: 0.4 ui ami data displacement for t1 and 0.2 ui ami data displacement for e1. 33. at max load of 1.6 ma and 50 pf. 34. host mode (clke = 1). 35. extended hardware mode. 36. the maximum tclk burst rate is 5 mhz and t pw2 (min) = 200 ns. the maximum gap size that can be tolerated on tclk is 12 vi. 37. the transmitted pulse width does not depend on the tclk duty cycle. rclk t pw1 t pwl1 t pwh1 host mode (clke = 1) extended hardware mode or hardware host mode (clke = 0) mode or rclk rpos rneg su1 h1 tt rdata bpv figure 1. recovered clock and data switching characteristics cs61535a 6 ds40f2
e1 switching characteristics (ta = -40 c to 85 c; tv+, rv+ = 5.0v 5%; gnd = 0v; inputs: logic 0 = 0v, logic 1 = rv+; see figures 1, 2, & 3) parameter symbol min typ max units crystal frequency (note 29) f c - 8.192000 - mhz aclki duty cycle t pwh3 /t pw3 40 - 60 % aclki frequency (note 30) f aclki -2.048-mhz rclk duty cycle (notes 31, 32) t pwh1 /t pw1 -29-% rclk cycle width (note 32) t pw1 t pwh1 t pwl1 310 90 120 488 140 348 670 190 500 ns ns ns rclk cycle width (note 32) t pw1 t pwh1 t pwl1 320 - 100 488 348 140 670 - - ns ns ns rise time, all digital outputs (note 33) t r - - 85 ns fall time, all digital outputs (note 33) t f - - 85 ns tpos/tneg (tdata) to tclk falling setup time t su2 25 - - ns tclk falling to tpos/tneg (tdata) hold time t h2 25 - - ns rpos/rneg valid before rclk falling (note 34) t su1 100 194 - ns rdata valid before rclk falling (note 35) t su1 100 194 - ns rpos/rneg valid before rclk rising (note 31) t su1 100 194 - ns rpos/rneg valid after rclk falling (note 34) t h1 100 194 - ns rdata valid after rclk falling (note 35) t h1 100 194 - ns rpos/rneg valid after rclk rising (note 31) t h1 100 194 - ns tclk frequency f tclk -2.048-mhz tclk pulse width (notes 31, 34, 36, 37) (notes 35, 36, 37) t pwh2 80 150 - - 340 340 ns ns tclk tpos/tneg t su2 t h2 t pwh2 t pw2 figure 3a. transmit clock and data switching characteristics aclki t pwh3 t pw3 figure 3b. alternate external clock characteristics any digital output t r t f 10% 10% 90% 90% figure 2. signal rise and fall characteristics cs61535a ds40f2 7
switching characteristics (ta = -40 to 85 c; tv+, rv+ = 5%; inputs: logic 0 = 0v, logic 1 = rv+) parameter symbol min typ max units sdi to sclk setup time t dc 50 - - ns sclk to sdi hold time t cdh 50 - - ns sclk low time t cl 240 - - ns sclk high time t ch 240 - - ns sclk rise and fall time t r , t f - - 50 ns cs to sclk setup time t cc 50 - - ns sclk to cs hold time (note 38) t cch 50 - - ns cs inactive time t cwh 250 - - ns sclk to sdo valid (note 39) t cdv - - 200 ns cs to sdo high z t cdz - 100 - ns input valid to pcs falling setup time t su4 50 - - ns pcs rising to input invalid hold time t h4 50 - - ns pcs active low time t pcsl 250 - - ns notes: 38. for clke = 0, cs must remain low at least 50 ns after the 16 th falling edge of sclk. 39. output load capacitance = 50pf. t dc t cc lsb lsb msb control byte data byte cs sclk sdi t ch t cwh t cch t cdh t cl t cdh figure 4. serial port write timing diagram cs61535a 8 ds40f2
high z cs sclk sdo clke = 1 t cdz cdv t figure 5. serial port read timing diagram pcs valid input data len0/1/2, taos, rloop, lloop, t h4 t su4 t pcsl rcode, tcode figure 6. extended hardware mode parallel chip select timing diagram cs61535a ds40f2 9
theory of operation enhancements in cs61535a the cs61535a provides higher performance and more features than the cs61535 including: 50% lower power consumption, internally matched transmitter output imped- ance for improved signal quality, optional ami, b8zs, hdb3 encoder/decoder or external line coding support, receiver ais (unframed all ones) detection, ansi t1.231-1993 compliant receiver loss of signal (los) handling, transmitter ttip and tring outputs are forced low when tclk is static, the driver performance monitor operates over a wider range of input signal levels. elimination of the requirement that a refer- ence clock be input on the aclki pin. existing designs using the cs61535 can be converted to the higher performance, pin-compatible cs61535a if the transmit transformer is replaced by a pin-com- patible transformer with a new turns ratio and the 4.4 w resistor used in e1 75 w applications is shorted. introduction to operating modes the cs61535a supports three operating modes which are selected by the level of the mode pin as shown in tables 1 and 2, figure 7, and figures a1-a3 of the applications section. the cs61535a modes are hardware mode, ex- tended hardware mode, and host mode. in hardware and extended hardware modes, discrete pins are used to configure and monitor the device. the extended hardware mode provides a parallel chip select input which latches the control inputs allowing individual ics to be configured using a common set of control lines. in the host mode, an external processor monitors and configures the de- vice through a serial interface. there are thirteen multi-function pins whose functionality is deter- mined by the operating mode (see table 2). transmitter the transmitter takes data from a t1 (or e1) ter- minal, attenuates jitter, and produces pulses of appropriate shape. the transmit clock, tclk, and transmit data, tpos & tneg or tdata, are supplied synchronously. data is sampled on the falling edge of the input clock, tclk. either t1 (dsx-1 or network interface) or e1 g.703 pulse shapes may be selected. pulse shap- ing and signal level are determined by "line length select" inputs as shown in table 3. the mode hardware extended hardware host mode-pin input level <0.2v float, or 2.5v >(rv+) - 0.2v control method individual control lines individual control lines & parallel chip select serial m -processor port line code encoder & decoder none ami, b8zs, hdb3 none ais detection no yes no driver perform- ance monitor yes no yes table 1. differences in operating modes mode function pin hardware extended hardware host transmitter 3tpos tdata tpos 4tneg tcode tneg receiver/dpm 6 rneg bpv rneg 7 rpos rdata rpos 11 dpm ais dpm 17 mtip rcode mtip 18 mring - mring control 18 - pcs - 23 len0 len0 int 24 len1 len1 sdi 25 len2 len2 sdo 26 rloop rloop cs 27 lloop lloop sclk 2 8 ta os tao s cl ke table 2. pin definitions cs61535a 10 ds40f2
tpos tneg rneg rpos transmit transformer rring receive transformer control cs62180b framer circuit ttip tdata rdata tring line driver ami b8zs, hdb3, coder transmit transformer rloop pcs len0/1/2 lloop taos control hardware mode extended hardware mode host mode control 5 m p serial port rcode tcode clke bpv ais jitter attenuator driver monitor line driver line receiver mtip mring dpm rtip ttip tring high speed mux (e.g., m13) cs61535a cs61535a ttip tpos tneg rneg tring rpos rring rtip rloop len0/1/2 lloop taos control dpm driver monitor line driver line receiver mtip mring cs61535a cs62180b framer circuit transmit transformer receive transformer receive transformer rring rtip ais detect jitter attenuator line receiver jitter attenuator figure 7. overview of operating modes cs61535a ds40f2 11
cs61535a line driver is designed to drive a 75 w equivalent load. for t1 dsx-1 applications, line lengths from 0 to 655 feet (as measured from the transmitter to the dsx-1 cross connect) are selectable. the five partition arrangement meets ansi t1.102-1993 requirements when using abam cable. a typical output pulse is shown in figure 8. these pulse settings can also be used to meet ccitt pulse shape requirements for 1.544 mhz operation. for t1 network interface applications, additional options are provided. note that the optimal pulse width for part 68 (324 ns) is narrower than the optimal pulse width for dsx-1 (350 ns). the cs61535a automatically adjusts the pulse width based upon the "line length " selection made. the e1 g.703 pulse shape is supported with line length selection len2/1/0=0/0/0. the pulse width will meet the g.703 pulse shape template shown in figure 9, and specified in table 4. for e1 applications, the cs61535a driver pro- vides 14 db of return loss during the transmission of both marks and spaces. this improves signal quality by minimizing reflections off the trans- mitter. similar levels of return loss are provided for t1 applications. the cs61535a transmitter will detect a failed tclk, and will force the ttip and tring out- puts low. 500 1.0 0.5 0 -0.5 0 250 750 1000 normalized amplitude at&t cb 119 specification cs61535a pulse shape output time (nanoseconds) figure 8. typical pulse shape at dsx-1 cross connect len2 len1 len0 option selected application 0 1 1 0-133 feet dsx-1 abam (at&t 600b or 600c) 100 133-266 feet 101 266-399 feet 110 399-533 feet 111 533-655 feet 001 at&t cb113 (cs61535a only) repeater 0 0 0 ccitt g.703 2.048 mhz e1 0 1 0 fcc part 68, option a csu network interface 0 1 1 ansi t1.403 table 3. line length selection for coaxial cable, 75 w load and transformer specified in application section. for shielded twisted pair, 120 w load and transformer specified in application section. nominal peak voltage of a mark (pulse) 2.37 v 3 v peak voltage of a space (no pulse) 0 0.237 v 0 0.30 v nominal pulse width 244 ns ratio of the amplitudes of positive and negative pulses at the center of the pulse interval 0.95 to 1.05* ratio of the widths of positive and negative pulses at the nominal half amplitude 0.95 to 1.05* * when configured with a 0.47 m f nonpolarized capacitor in series with the tx transformer primary as shown in figures a1, a2 and a3. table 4. ccitt g.703 specifications cs61535a 12 ds40f2
when any transmit control pin (taos, len0-2 or lloop) is toggled, the transmitter stabilizes within 22 bit periods. the transmitter will take longer to stabilize when rloop is selected be- cause the timing circuitry must adjust to the new frequency. jitter attenuator the jitter attenuator is designed to reduce wander and jitter in the transmit clock signal. it consists of a 32 bit fifo, a crystal oscillator, a set of load capacitors for the crystal, and control logic. the jitter attenuator exceeds the jitter attenuation re- quirements of publications 43802 and rec. g.742. a typical jitter attenuation curve is shown in figure 10. the jitter attenuator works in the following man- ner. data on tpos and tneg (or tdata) are written into the jitter attenuators fifo by tclk. the rate at which data is read out of the fifo and transmitted is determined by the oscillator. logic circuits adjust the capacitive loading on the crys- tal to set its oscillation frequency to the average of the tclk frequency. signal jitter is absorbed in the fifo. jitter tolerance of jitter attenuator the fifo in the jitter attenuator is designed to neither overflow nor underflow. if the jitter am- plitude becomes very large, the read and write pointers may get very close together. should the pointers attempt to cross, the oscillators divide by four circuit adjusts by performing a divide by 3 1/2 or divide by 4 1/2 to prevent the overflow or underflow. when a divide by 3 1/2 or 4 1/2 occurs, the data bit will be driven on to the line either an eighth bit period early or an eighth bit period late. when the tclk frequency is close to the center frequency of the crystal oscillator, the high fre- quency jitter tolerance is 23 ui before the divide by 3 1/2 or 4 1/2 circuitry is activated. as the center frequency of the oscillator and the tclk frequency deviate from one another, the jitter tol- erance is reduced. as this frequency deviation becomes large, the maximum jitter tolerance at high frequencies is reduced to 12 ui before the underflow/overflow circuitry is activated. in ap- plication, it is unlikely that the oscillator center frequency will be precisely aligned with the attenuation in db frequency in hz 0 10 20 30 40 50 60 1 10 100 1 k 10 k b) maximum attenuation limit at&t 62411 requirements a) minimum attenuation limit measured performance figure 10. typical jitter attenuation curve 269 ns 244 ns 194 ns 219 ns 488 ns nominal pulse 0 10 50 80 90 100 110 120 -10 -20 percent of nominal peak voltage figure 9 . mask of the pulse at the 2048 kbps interface cs61535a ds40f2 13
tclk frequency due to allowable tclk toler- ance, part to part variations, crystal to crystal variations, and crystal temperature drift. the os- cillator tends to track low frequency jitter so jitter tolerance increases as jitter frequency decreases. the crystal frequency must be 4 times the nomi- nal signal frequency: 6.176 mhz for 1.544 mhz operation; 8.192 mhz for 2.048 mhz applica- tions. internal capacitors load the crystal, controlling the oscillation frequency. the crystal must be designed so that over operating tempera- ture, the oscillator frequency range exceeds the system frequency tolerance. crystal semiconduc- tor offers the cxt6176 & cxt8192 crystals, which yield optimum performance with the cs61535a. transmit all ones select the transmitter provides for all ones insertion at the frequency of aclki. transmit all ones is se- lected when taos goes high, and causes continuous ones to be transmitted on the line (ttip and tring). in this mode, the tpos and tneg (or tdata) inputs are ignored. a taos request will be ignored if remote loopback is in effect. aclki jitter will be attenuated. taos is not available on the cs61535a when aclki is grounded. receiver the receiver extracts data and clock from an ami (alternate mark inversion) coded signal and out- puts clock and synchronized data. the receiver is sensitive to signals over the entire range of cable lengths and requires no equalization or albo (automatic line build out) circuits. the signal is received on both ends of a center-tapped, center- grounded transformer. the transformer is center-tapped on the ic side. the clock and data recovery circuit exceeds the jitter tolerance speci- fications of publications 43802, 43801, 62411 amended, tr-tsy-000170, and ccitt rec. g.823. a block diagram of the receiver is shown in fig- ure 11. the two leads of the transformer (rtip and rring) have opposite polarity allowing the receiver to treat rtip and rring as unipolar sig- nals. comparators are used to detect pulses on rtip and rring. the comparator thresholds are dynamically established at a percent of the peak level (50% of peak for e1, 65% of peak for t1; with the slicing level selected by len2/1/0). 1 : 2 rtip rring rpos rneg rclk aclki or oscillator in jitter attenuator data level slicer edge detector data & clock sampling extraction clock phase selector continuously calibrated delay line figure 11. receiver block diagram cs61535a 14 ds40f2
the receiver uses an edge detector and a continu- ously calibrated delay line to generate the recovered clock. the delay line divides its refer- ence clock, aclki or the jitter attenuators oscillator, into 13 equal divisions or phases. con- tinuous calibration assures timing accuracy, even if temperature or power supply voltage fluctuate. the leading edge of an incoming data pulse trig- gers the clock phase selector. the phase selector chooses one of the 13 available phases which the delay line produces for each bit period. the out- put from the phase selector feeds the clock and data recovery circuits which generate the recov- ered clock and sample the incoming signal at appropriate intervals to recover the data. the jitter tolerance of the receiver exceeds that shown in figure 12. the cs61535a outputs a clock immediately upon power-up. the clock recovery circuit is cali- brated, and the device will lock onto the ami data input immediately. if loss of signal occurs, the rclk frequency will equal the aclki fre- quency. in the hardware mode, data at rpos and rneg is stable and may be sampled on the rising edge of the recovered clock. in the extended hardware mode, data at rdata is stable and may be sam- pled on the falling edge of the recovered clock. in the host mode, clke determines the clock po- larity for which output data is stable and valid as shown in table 5. jitter and recovered clock the cs61535a are designed for error free clock and data recovery from an ami encoded data stream in the presence of more than 0.4 unit inter- vals of jitter at high frequency. the clock recovery circuit is also tolerant of long strings of zeros. the edge of an incoming data bit causes the circuitry to choose a phase from the delay line which most closely corresponds with the arrival time of the data edge, and that clock phase trig- gers a pulse which is typically 140 ns in duration. this phase of the delay line will continue to be selected until a data bit arrives which is closer to another of the 13 phases, causing a new phase to be selected. the largest jump allowed along the delay line is six phases. when an input signal is jitter free, the phase se- lection will occasionally jump between two adjacent phases resulting in rclk jitter with an amplitude of 1/13 uipp. these single phase jumps are due to differences in frequency of the incoming data and the calibration clock input to aclki. for t1 operation of the cs61535a, the instantaneous period can be 14/13 * 648 ns = 698 ns (1,662,769 hz) or 12/13 * 648 ns = 598 ns (1,425,231 hz) when adjacent clock phases are chosen. as long as the same phase is chosen, the 10 1k 10k 0 100 100k 700 .1 1 10 100 .4 28 300 300 peak to peak jitter (unit intervals) jitter frequency (hz) figure 12. input jitter tolerance of receiver mode (pin 5) clke (pin 28) data clock clock edge for valid data low (<0.2v) xrpos rneg rclk rclk rising rising high (>(v+) - 0.2v) low rpos rneg sdo rclk rclk sclk rising rising falling high (>(v+) - 0.2v) high rpos rneg sdo rclk rclk sclk falling falling rising middle (2.5v) x rdata rclk falling x = don?t care table 5. data output/clock relationship cs61535a ds40f2 15
period will be 648 ns. similar calculations hold for the e1 rate. the clock recovery circuit is designed to accept at least 0.4 ui of jitter at the receiver. since the data stream contains information only when ones are transmitted, a clock/data recovery circuit must as- sume a zero when no signal is measured during a bit period. likewise, when zeros are received, no information is present to update the clock recov- ery circuit regarding the trend of a signal which is jittered. the result is that two ones that are sepa- rated by a string of zeros can exhibit maximum deviation in pulse arrival time. for example, one half of a period of jitter at 100 khz occurs in 5 m s, which is 7.7 t1 bit periods. if the jitter ampli- tude is 0.4 ui, then a one preceded by seven zeros can have maximum displacement in arrival time, i.e. either 0.4 ui too early or 0.4 ui too late. for the cs61535a, the data recovery circuit correctly assigns a received bit to its proper clock period if it is displaced by less than 6/13 of a bit period from its optimal location. theoretically, this would give a jitter tolerance of 0.46 ui. the ac- tual jitter tolerance of the cs61535a is only slightly less than the ideal. in the event of a maximum jitter hit, the rclk clock period immediately adjusts to align itself with the incoming data and prepare to accurately place the next one, whether it arrives one period later, or after another string of zeros and is dis- placed by jitter. for a maximum early jitter hit, rclk will have a period of 7/13 * 648 ns = 349 ns (2,865,961 hz). for a maximum late jitter hit, rclk will have a period of 19/13 * 648 ns = 947 ns (1,055,880 hz). loss of signal receiver loss of signal is indicated upon receiv- ing 175 consecutive zeros. a digital counter counts received zeros based on rclk cycles. a zero input is determined either when zeros are re- ceived, or when the received signal amplitude drops below a 0.3 v peak threshold. the receiver reports loss of signal by setting the loss of signal pin, los, high. if the serial inter- face is used, the los bit will be set and an interrupt issued on int. los will go low (and flag the int pin again if serial i/o is used) when a valid signal is detected. note that in the host mode, los is simultaneously available from both the register and pin 12. in a loss of signal state, the rclk frequency will be equal to the aclki frequency since aclki is being used to calibrate the clock recovery circuit. received data is output on rpos and rneg (or rdata) regardless of los status. the los re- turns to logic zero when the ones density reaches 12.5% (based upon 175 bit periods staring with a one and containing less than 100 consecutive ze- ros) as prescribed in ansi t1.231-1993. a power-up or manual reset will also set los high. local loopback the local loopback mode takes clock and data presented on tclk, tpos, and tneg (or tdata) and outputs it at rclk, rpos and rneg (or rdata). local loopback is selected by taking pin 27 high, or lloop may be selected using the serial interface. the data on the trans- mitter inputs is transmitted on the line unless taos is selected to cause the transmission of an all ones signal instead. receiver inputs are ig- nored when local loopback is in effect. the jitter attenuator is not included in the local loopback data path. selection of local loopback overrides the chips loss of signal response. remote loopback in remote loopback, the recovered clock and data input on rtip and rring are sent through the jitter attenuator and back out on the line via ttip and tring. the recovered incoming signals are also sent to rclk, rpos and rneg (or cs61535a 16 ds40f2
rdata). remote loopback is selected by taking pin 26 high, or rloop may be selected using the serial interface. simultaneous selection of local and remote loopback modes is not valid (see re- set). in the cs61535a extended hardware mode, re- mote loopback occurs before the line code encoder/decoder, insuring that the transmitted sig- nal matches the received signal, even in the presence of received bipolar violations. the re- covered data will also be decoded and output on rdata if rcode is low. driver performance monitor to aid in early detection and easy isolation of nonfunctioning links, the hardware and host modes of the cs61535a are able to monitor transmit drive performance and report when the driver is no longer operational. this feature can be used to monitor either the devices perform- ance or the performance of a neighboring driver. the driver performance monitor indicator is nor- mally at a low (zero) logic level, and goes to high level upon detecting driver failure. in the host mode, dpm is available from both the register and pin 11. the driver performance monitor consists of an ac- tivity detector that monitors the transmitted signal when mtip is connected to ttip and mring is connected to tring. dpm will go high if the absolute difference between mtip and mring does not transition above or below a threshold level within a time-out period. whenever more than one line interface ic resides on the same circuit board, the effectiveness of the driver performance monitor can be maximized by having each ic monitor performance of a neigh- boring device, rather than having it monitor its own performance. line code encoder/decoder in extended hardware mode, three line codes are available: ami, b8zs and hdb3. the input to the encoder is tdata. the outputs from the de- coder are rdata and bpv (bipolar violation strobe). the encoder and decoder are selected us- ing pins len2, len1, len0, tcode and rcode as shown in table 6. alarm indication signal in extended hardware mode, the receiver sets the output pin ais high when less than 9 zeros are detected out of 8192 bit periods. ais returns low when 9 or more zeros are detected out of 8192 bits. parallel chip select in extended hardware mode, pcs can be used to gate the digital control inputs: tcode, rcode, len0, len1, len2, rloop, lloop and taos. inputs are accepted on these pins only when pcs is low. changes in inputs will immedi- ately change the operating state of the device. therefore, when cycling pcs to update the oper- ating state, the digital control inputs should be stable for the entire pcs low period. the control inputs are ignored when pcs is high. power on reset / reset upon power-up, the cs61535a is held in a static state until the supply crosses a threshold of ap- len 2/1/0 000 010-111 tcode (transmit encoder selection) low hdb3 encoder b8zs encoder high ami encoder rcode (receiver decoder selection) low hdb3 decoder b8zs decoder high ami decoder table 6. selection of encoder/decoder cs61535a ds40f2 17
proximately three volts. when this threshold is crossed, the device will delay for about 10 ms to allow the power supply to reach operating voltage. after this delay, calibration of the delay lines used in the transmit and receive sections commences. the delay lines can be calibrated only if a refer- ence clock is present. the reference clock for the receiver is provided by aclki (or by the crystal oscillator if aclki is not present). the reference clock for the transmitter is provided by tclk. the initial calibration should take less than 20 ms. in operation, the delay lines are continuously cali- brated, making the performance of the device independent of power supply or temperature vari- ations. the continuous calibration function foregoes any requirement to reset the line inter- face when in operation. however, a reset function is available which will clear all registers. in the hardware and extended hardware modes, a reset request is made by simultaneously setting both rloop and lloop high for at least 200 ns. reset will initiate on the falling edge of the reset request (falling edge of rloop and lloop). in the host mode, a reset is initiated by simultaneously writing rloop and lloop to the register. in either mode, a reset will set all registers to 0 and set los high. serial interface in the host mode, pins 23 through 28 serve as a microprocessor/microcontroller interface. one eight-bit register can be written to via the sdi pin or read from the sdo pin at the clock rate deter- mined by sclk. through this register, a host controller can be used to control operational char- acteristics and monitor device status. the serial port read/write timing is independent of the sys- tem transmit and receive timing. data transfers are initiated by taking the chip se- lect input, cs, low ( cs must initially be high). sclk may be either high or low when cs in- itially goes low. address and input data bits are clocked in on the rising edge of sclk. data on sdo is valid and stable on the falling edge of sclk when clke is low, and on the rising edge of sclk when clke is high. data transfers are terminated by setting cs high. cs may go high no sooner than 50 ns after the rising edge of the sclk cycle corresponding to the last write bit. for a serial data read, cs may go high any time to terminate the output. figure 13 shows the timing relationships for data transfers when clke = 1. when clke = 0, data output from the serial port, sdo, is valid on the falling edge of sclk. for clke = 1, data bit d7 is held to the falling edge of the 16th clock cycle; for clke = 0, data bit d7 is held to the rising edge of the 17th clock cycle. sdo goes to a high cs sclk sdo sdi d6 d5 d4 d3 d2 d1 d0 d7 0 0 d7 d6 d5 d4 d3 d2 d1 d0 address/command byte data input/output 0 0 0 1 0 r/w figure 13. input/output timing lsb, first bit 0 r/ w read/write select; 0 = write, 1 = read 1 add0 lsb of address, must be 0 2 add1 must be 0 3 add2 must be 0 4 add3 must be 0 5 add4 must be 1 6 - reserved - must be 0 table 7. address/command byte cs61535a 18 ds40f2
impedance state either after bit d7 is output or at the end of the hold period of data bit d7. an address/command byte, shown in table 7, precedes a data register. the first bit of the ad- dress/command byte determines whether a read or a write is requested. the next six bits contain the address. the cs61535a responds to address 16 (0010000). the last bit is ignored. the data register, shown in table 8, can be writ- ten to the serial port. data is input on the eight clock cycles immediately following the ad- dress/command byte. bits 0 and 1 are used to clear an interrupt issued from the int pin, which occurs in response to a loss of signal or a problem with the output driver. if bits 0 or 1 are true, the corresponding interrupt is suppressed. so if a loss of signal interrupt is cleared by writing a 1 to bit 0, the interrupt will be reenabled by writing a 0 to bit 0. this holds for dpm as well. writing a "1" to either "clear los" or "clear dpm" over the serial interface has three effects: 1) the current interrupt on the serial interface will be cleared. (note that simply reading the register bits will not clear the interrupt), 2) output data bits 5, 6 and 7 will be reset as appropriate, 3) future interrupts for the corresponding los or dpm will be prevented from occuring). writing a "0" to either "clear los" or "clear dpm" enables the corresponding interrupt for los or dpm. output data from the serial interface is presented as shown in tables 9 and 10. bits 2, 3 and 4 can be read to verify line length selection. bits 5, 6 and 7 must be decoded. codes 101, 110 and 111 (bits 5, 6 and 7) indicate los and dpm state changes. writing a "1" to the "clear los" and/or "clear dpm" bits in the register also resets status bits 5, 6, and 7. sdo goes to a high impedance state when not in use. sdo and sdi may be tied together in appli- cations where the host processor has a bidirectional i/o port. lsb: first bit in 0 clr los clear loss of signal 1 clr dpm clear driver performance monitor 2 len0 bit 0 - line length select 3 len1 bit 1 - line length select 4 len2 bit 2 - line lenght select 5 rloop remote loopback 6 lloop local loopback msb: last bit in 7 taos transmit all ones select table 8. input data register lsb: first bit in 0 los loss of signal 1 dpm driver performance monitor 2 len0 bit 0 - line length select 3 len1 bit 1 - line length select 4 len2 bit 2 - line lenght select table 9. output data bits 0 - 4 bits status 567 000 reset has occurred or no program input. 001 taos in effect. 010 lloop in effect. 011 taos/lloop in effect. 100 rloop in effect 101 dpm changed state since last "clear dpm" occured. 110 los changed state since last "clear los" occured. 111 los and dpm have changed state since last "clear los" and "clear dpm". table 10. coding for serial output bits 5, 6, 7 cs61535a ds40f2 19
power supply the device operates from a single +5 volt supply. separate pins for transmit and receive supplies provide internal isolation. these pins should be connected externally near the device and decou- pled to their respective grounds. tv+ must not exceed rv+ by more than 0.3v. decoupling and filtering of the power supplies is crucial for the proper operation of the analog cir- cuits in both the transmit and receive paths. a 1.0 m f capacitor should be connected between tv+ and tgnd, and a 0.1 m f capacitor should be con- nected between rv+ and rgnd. use mylar or ceramic capacitors and place them as closely as possible to their respective power supply pins. a 68 m f tantalum capacitor should be added close to the rv+/rgnd supply. wire wrap bread- boarding of the line interface is not recommended because lead resistance and inductance serve to defeat the function of the decoupling capacitors. schematic & layout review service confirm optimum schematic & layout before building your board. for our free review service call applications engineering. call: (512) 445-7222 cs61535a 20 ds40f2
pin descriptions hardware mode top view 22 20 24 19 21 23 25 327 2 426 28 1 12 14 16 18 13 15 17 8 6 10 5 7 9 11 aclki tclk taos tpos lloop tneg rloop mode len2 rneg len1 rpos len0 rclk rgnd xtalin rv+ xtalout rring dpm rtip los mring ttip mtip tgnd tring tv+ 1 2 3 4 5 6 7 8 9 10 11 12 14 13 28 27 26 25 24 23 22 21 20 19 18 17 16 15 aclki taos tclk lloop tpos rloop tneg len2 mode len1 rneg len0 rpos rgnd rclk rv+ xtalin rring xtalout rtip dpm mring los mtip ttip tring tgnd tv+ cs61535a ds40f1 21
extended hardware mode 1 2 3 4 5 6 7 8 9 10 11 12 14 13 28 27 26 25 24 23 22 21 20 19 18 17 16 15 aclki taos tclk lloop tdata rloop tcode len2 mode len1 bpv len0 rdata rgnd rclk rv+ xtalin rring xtalout rtip ais pcs los rcode ttip tring tgnd tv+ top view 22 20 24 19 21 23 25 327 2 426 28 1 12 14 16 18 13 15 17 8 6 10 5 7 9 11 aclki tclk taos tdata lloop tcode rloop mode len2 bpv len1 rdata len0 rclk rgnd xtalin rv+ xtalout rring ais rtip los pcs ttip rcode tgnd tring tv+ cs61535a 22 ds40f1
host mode 1 2 3 4 5 6 7 8 9 10 11 12 14 13 28 27 26 25 24 23 22 21 20 19 18 17 16 15 aclki clke tclk sclk tpos cs tneg sdo mode sdi rneg int rpos rgnd rclk rv+ xtalin rring xtalout rtip dpm mring los mtip ttip tring tgnd tv+ top view 22 20 24 19 21 23 25 327 2 426 28 1 12 14 16 18 13 15 17 8 6 10 5 7 9 11 aclki tclk clke tpos sclk tneg cs mode sdo rneg sdi rpos int rclk rgnd xtalin rv+ xtalout rring dpm rtip los mring ttip mtip tgnd tring tv+ cs61535a ds40f1 23
power supplies rgnd - ground, pin 22. power supply ground for all subcircuits except the transmit driver; typically 0 volts. rv+ - power supply, pin 21. power supply for all subcircuits except the transmit driver; typically +5 volts. tgnd - ground, transmit driver, pin 14. power supply ground for the transmit driver; typically 0 volts. tv+ - power supply, transmit driver, pin 15. power supply for the transmit driver; typically +5 volts. tv+ must not exceed rv+ by more than 0.3 v. oscillator xtalin, xtalout - crystal connections, pins 9 and 10. a 6.176 mhz (or 8.192 mhz) crystal should be connected across these pins. if a 1.544 mhz (or 2.048 mhz) clock is provided on aclki (pin 1), the jitter attenuator may be disabled by tying xtalin, pin 9 to rv+ through a 1 k w resistor, and floating xtalout, pin 10. overdriving the oscillator with an external clock is not supported. control aclki - alternate external clock input, pin 1. the cs61535a does not require a clock signal to be input on aclki when a crystal is connected between pins 9 and 10. if a clock is not provided on aclki, this input must be grounded. if aclki is grounded, the oscillator in the jitter attenuator is used to calibrate the clock recovery circuit and taos is not available. clke - clock edge, pin 28. (host mode) setting clke to logic 1 causes rpos and rneg to be valid on the falling edge of rclk, and sdo to be valid on the rising edge of sclk. conversely, setting clke to logic 0 causes rpos and rneg to be valid on the rising edge of rclk, and sdo to be valid on the falling edge of sclk. cs - chip select, pin 26. (host mode) this pin must transition from high to low to read or write the serial port. int - receive alarm interrupt, pin 23. (host mode) goes low when los or dpm change state to flag the host processor. int is cleared by writing "clear los" or "clear dpm" to the register. int is an open drain output and should be tied to the power supply through a resistor. cs61535a 24 ds40f1
len0, len1, len2 - line length selection, pins 23, 24 and 25. (hardware and extended hardware modes) determines the shape and amplitude of the transmitted pulse to accommodate several cable types and lengths. see table 3 for information on line length selection. also controls the receiver slicing level and the line code in extended hardware mode. lloop - local loopback, pin 27. (hardware and extended hardware modes) setting lloop to a logic 1 routes the transmit clock and data through to the receive clock and data pins. tpos/tneg (or tdata) are still transmitted unless overridden by a taos request. inputs on rtip and rring are ignored. mode - mode select, pin 5. driving the mode pin high puts the cs61535a line interface in the host mode. in the host mode, a serial control port is used to control the cs61535a line interface and determine its status. grounding the mode pin puts the cs61535a line interface in the hardware mode, where configuration and status are controlled by discrete pins. floating the mode pin or driving it to +2.5 v puts the cs61535a in extended hardware mode, where configuration and status are controlled by discrete pins. when floating mode, there should be no external load on the pin. mode defines the status of 13 pins (see table 2). pcs - parallel chip select, pin 18. (extended hardware mode) setting pcs high causes the cs61535a line interface to ignore the tcode, rcode, len0, len1, len2, rloop, lloop and taos inputs. rcode - receiver decoder select, pin 17. (extended hardware mode) setting rcode low enables b8zs or hdb3 zero substitution in the receiver decoder. setting rcode high enables the ami receiver decoder (see table 8). rloop - remote loopback, pin 26. (hardware and extended hardware modes) setting rloop to a logic 1 causes the recovered clock and data to be sent through the jitter attenuator (if active) and through the driver back to the line. the recovered signal is also sent to rclk and rpos/rneg (or rdata). any taos request is ignored. simultaneously taking rloop and lloop high for at least 200 ns initiates a device reset. sclk - serial clock, pin 27. (host mode) clock used to read or write the serial port registers. sclk can be either high or low when the line interface is selected using the cs pin. sdi - serial data input, pin 24. (host mode) data for the on-chip register. sampled on the rising edge of sclk. sdo - serial data output, pin 25. (host mode) status and control information from the on-chip register. if clke is high sdo is valid on the rising edge of sclk. if clke is low sdo is valid on the falling edge of sclk. this pin goes to a high-impedance state when the serial port is being written to or after bit d7 is output. cs61535a ds40f1 25
taos - transmit all ones select, pin 28. (hardware and extended hardware modes) setting taos to a logic 1 causes continuous ones to be transmitted at the frequency determined by aclki. tcode - transmitter encoder select, pin 4. (extended hardware mode) setting tcode low enables b8zs or hdb3 zero substitution in the transmitter encoder. setting tcode high enables the ami transmitter encoder . data rclk - recovered clock, pin 8. the receiver recovered clock is output on this pin. rdata - receive data - pin 7. (extended hardware mode) data recovered from the rtip and rring inputs is output at this pin, after being decoded by the line code decoder. rdata is nrz. rdata is stable and valid on the falling edge of rclk. rpos, rneg - receive positive data, receive negative data, pins 6 and 7. (hardware and host modes) the receiver recovered nrz digital data is output on these pins. in the hardware mode, rpos and rneg are stable and valid on the rising edge of rclk. in the host mode, clke determines the clock edge for which rpos and rneg are stable and valid. see table 5. a positive pulse (with respect to ground) received on the rtip pin generates a logic 1 on rpos, and a positive pulse received on the rring pin generates a logic 1 on rneg. rtip, rring - receive tip, receive ring, pins 19 and 20. the ami receive signal is input to these pins. a center-tapped, center-grounded, 2:1, step-up transformer is required on these inputs, as shown in figure a1 in the applications section. data and clock are recovered and output on rclk and rpos/rneg or rdata. tclk - transmit clock, pin 2. the1.544 mhz (or 2.048 mhz) transmit clock is input on this pin. tpos/tneg or tdata are sampled on the falling edge of tclk. tdata - transmit data, pin 3. (extended hardware mode) transmitter nrz input data which passes through the line code encoder, and is then driven on to the line through ttip and tring. tdata is sampled on the falling edge of tclk. tpos, tneg - transmit positive data, transmit negative data, pins 3 and 4. (hardware and host modes) inputs for clock and data to be transmitted. the signal is driven on to the line through ttip and tring. tpos and tneg are sampled on the falling edge of tclk. a tpos input causes a positive pulse to be transmitted, while a tneg input causes a negative pulse to be transmitted. ttip, tring - transmit tip, transmit ring, pins 13 and 16. the ami signal is driven to the line through these pins. in the cs61535a, this output is designed to drive a 75 w load. a 1:1, 1:1.15 or 1:1.26 transformer is required as shown in figure a1. cs61535a 26 ds40f1
status ais - alarm indication signal, pin 11. (extended hardware mode) ais goes high when unframed all-ones condition (blue alarm) is detected, using the detection criteria of less than three zeros out of 2048 bit periods. bpv- bipolar violation strobe, pin 6. (extended hardware mode) bpv strobes high when a bipolar violation is detected in the received signal. b8zs (or hdb3) zero substitutions are not flagged as bipolar violations if the b8zs (or hdb3) decoder has been enabled. dpm - driver performance monitor, pin 11. (hardware and host modes) dpm goes high if no activity is detected on mtip and mring. los - loss of signal, pin 12. los goes high when 175 consecutive zeros have been received. for the cs61535a, los returns low when the ones density reaches 12.5% (based upon 175 bit periods starting with a one and containing less than 100 consecutive zeros) as prescribed by ansi t1.231-1993. mtip, mring - monitor tip, monitor ring, pins 17 and 18. (hardware and host modes) these pins are normally connected to ttip and tring and monitor the output of a cs61535a. if the int pin in the host mode is used, and the monitor is not used, writing "clear dpm" to the serial interface will prevent an interrupt from the driver performance monitor. cs61535a ds40f1 27
28 pin plastic dip 1 28 15 14 millimeters inches dim min max min max d b a l c 13.72 14.22 0.540 0.560 36.45 1.02 0.36 0.51 3.94 3.18 0.20 0 15.24 37.21 1.65 0.56 1.02 5.08 3.81 0.38 15 1.435 0.040 0.014 0.020 0.155 0.125 0.600 0.008 0 1.465 0.065 0.022 0.040 0.200 0.150 0.015 15 15.87 0.625 2.41 2.67 0.095 0.105 c ea e1 d b seating plane a b1 e1 a1 l notes: 1. positional tolerance of leads shall be within 0.25mm (0.010") at maximum material condition, in relation to seating plane and each other. 2. dimension ea to center of leads when formed parallel. 3. dimension e1 does not include mold flash. nom 13.97 36.83 1.27 0.46 0.76 4.32 - 0.25 - - 2.54 nom 0.550 1.450 0.050 0.018 0.030 0.170 - - 0.010 - 0.100 a1 b1 e1 e1 ea e e1 d1 d d2/e2 28-pin plcc 28 d2/e2 max min max min millimeters inches dim a 4.57 4.20 0.180 0.165 d/e 12.32 12.57 0.485 0.495 b 0.53 0.33 0.021 0.013 e a a1 b e 2.29 0.090 11.43 11.58 0.450 0.456 9.91 10.92 0.390 0.430 1.19 1.35 0.047 0.053 nom 4.45 12.45 0.41 2.79 11.51 10.41 1.27 nom 0.175 0.490 0.016 0.110 0.453 0.410 0.050 3.04 0.120 d1/e1 a1 cs61535a 28 ds40f1
applications line interface figures a1-a3 show the typical configurations for interfacing the i.c. to a line through transmit and receive transformers. the receiver transformer is center tapped and center grounded with resistors between the center tap and each leg on the i.c. side. these resistors provide the termination for the line. figures a1-a3 show a 0.47 m f capacitor in series with the transmit transformer primary. this ca- pacitor is needed to prevent any buildup in the core of the transformer due to any dc imbalance that may be present at the differential outputs, ttip and tring. if dc saturates the trans- former, a dc offset will result during the transmission of a space (zero) as the transformer tries to dump the charge and return to equilib- rium. the blocking capacitor will keep dc current from flowing in the transformer. selecting an oscillator crystal specific crystal parameters are required for proper operation of the cs61535a. it is recom- mended that the cxt6176 from crystal control & monitor frame format encoder/ decoder cs61535a in host mode receive line transmit line 28 1 12 11 5 7 6 8 3 4 2 9 10 xtl rv+ + 68 m f rgnd 0.1 m f +5v 21 15 + 1.0 m f tgnd rv+ tv+ clke aclki los dpm mode rpos rneg rclk tpos tneg tclk xtalin xtalout rgnd tgnd 22 14 sclk cs int sdi sdo rtip rring mtip mring tring ttip 19 20 17 18 16 13 r1 r2 0.47 m f ct 2:1 m p serial port 27 26 23 24 25 +5v 100 k w device frequency mhz cable w r1&2 w transmit transformer cs61535a 1.544 2.048 2.048 100 120 75 200 240 150 1:1.15 1:1.26 1:1 figure a1. host mode configuration cs61535a ds40f2 29
control & monitor frame format encoder/ decoder cs61535a in hardware mode line length setting receive line transmit line 28 1 26 27 5 7 6 8 3 4 2 9 10 xtl + 68 m f rgnd 0.1 m f +5v 21 15 + 1.0 m f tgnd rv+ tv+ taos aclki rloop lloop mode rpos rneg rclk tpos tneg tclk xtalin xtalout rgnd tgnd 22 14 len0 len1 len2 rtip rring mtip mring tring ttip 23 24 25 19 20 17 18 16 13 r1 r2 0.47 m f ct 2:1 12 11 los dpm figure a2. hardware mode configuration control & monitor frame format encoder/ decoder cs61535a in extended hardware mode line length setting receive line transmit line 17 18 6 28 5 7 8 3 2 9 10 xtl + 68 m f rgnd 0.1 m f +5v 21 15 + 1.0 m f tgnd rv+ tv+ rcode pcs bpv taos mode rdata rclk tdata tclk xtalin xtalout rgnd tgnd 22 14 len0 len1 len2 rtip rring tring ttip 23 24 25 19 20 16 13 r1 r2 0.47 m f ct 2:1 1 26 aclki rloop 27 12 lloop los 11 ais 4 tcode figure a3. extended hardware mode configuration cs61535a 30 ds40f2
semiconductor be used for t1 applications, and that the cxt8192 be used for e1 applications. interfacing the cs61535a with the cs62180b t1 transceiver to interface with the cs62180b, connect the de- vices as shown in figure a4. in this case, the cs61535a and cs62180b are in host mode con- trolled by a microprocessor serial interface. if the cs61535a is used in hardware mode, then the cs61535a rclk output must be inverted before being input to the cs62180b. if the cs61535a is used in extended hardware mode, the cs61535a rclk output does not need to be inverted before being input to the cs62180b. cs61534 compatibility the cs61535a is pin compatible with the cs61534. the cs61535a has greater jitter toler- ance for both transmitter and receiver, and it provides more jitter attenuation starting at jitter frequencies of 6 hz. the greater jitter tolerance and attenuation in the transmit path makes the cs61535a more suitable for ccitt demultiplex- ing applications where eight bits can be dropped from the clock/data stream at once. similarly, these parts can be used in sonet applications with the addition of some external circuitry. the main differences of the cs61535a relative to the cs61534 is: 1) on the cs61535a, selection of len 2/1/0 = 0/0/0 changes the voltage at which the receiver accepts an input as a pulse (slicing level) from 65% to 50% of the peak pulse amplitude. lower- ing the data slicing level will improve receiver sensitivity at long cable lengths when the data is jittered. a 50% slicing level will also improve crosstalk sensitivity for channels where received pulses do not have undershoot. 2) there are differences in the functionality of the aclki (aclk) input on the cs61534 and cs61535a. ackli (aclk) is used as the trans- mit clock in the transmit all ones (taos) mode. on the cs61535a, aclki is used as a calibra- tion reference for the receiver clock recovery circuit and therefore may not be supplied by rclk. on the cs61534, aclk may be supplied by rclk . if an external clock is not provide on the aclki input of the cs61535a, the crystal oscillator is used to calibrate the receiver clock recovery circuit. 3) on the cs61535a, the host mode status regis- ter bits 5, 6 and 7 are encoded so that state changes on los and dpm may be reported. 4) rclk on the cs61534 has a 50% duty cycle, while rclk on the cs61535a has a duty cycle which is typically 30% or 70%. also, the cs61535a rclk duty cycle and instantaneous frequency vary with received jitter and may ex- hibit 1/13 uipp quantization jitter even when the incoming signal is jitter free. 5) the cs61535a requires 25 ns of setup time on tpos and tneg before the falling edge of tclk and 25 ns of hold time on these inputs af- aclki tclk rgnd rclk rv+ +5v 0v 0.1uf rpos rneg tpos tneg cs62180b mode v+ clke sclk sdo sdi tclk tpos tneg rneg rpos rclk sclk sdo sdi to host controller v+ 100k 100k 1.544 mhz clock cs61535a cs v+ 22k signal 68uf + cs int figure a4. interfacing the cs61535a with the cs62180b (host mode) cs61535a ds40f2 31
ter the falling edge of tclk. the cs61534 re- quires 50 ns of hold time on tpos and tneg after the falling edge of tcl, and 0 ns of setup time. 6) los occurs after 31 consecutive zeros on the cs61534. for the cs61535a los occurs after 175 zeros. 7) since the cs61535a receivers are continu- ously calibrated, there is no need to issue a reset to initialize the receiver timing as with the cs61534. using the cs61535a for sonet the cs61535a can be applied to sonet vt1.5 and vt2.0 interface circuits as shown in fig- ure a5. the sonet data rate is 51.84 mhz, and has 6480 bits per frame (125 us per frame). an individual t1 frame (193 bits per frame) or pcm- 30 frame (256 bits per frame) has its data mapped into the 6480 bit sonet frame. the mapping does not result in a uniform spacing between sucessive t1 (or e1) bits. rather, for locked vt applications, gaps as large as 24 t1 bit periods or 32 e1 bit periods can exist between successive bits. with floating vts, the gaps can be even larger. the circuit in figure a5 eliminates the demulti- plexing jitter in a two-step approach. the first step uses a fifo which is filled at a 51.84 mhz rate (when t1 or e1 bits are present), and which is emptied at a sub-multiple of the 51.84 rate. the fifo is emptied only when it contains data. when the fifo is empty the output clock is not pulsed. the sub-multiple rate chosen should be slightly faster than the target rate (1.544 or 2.048 mhz), but as close to the target rate as possible. for tpos tclk2 tneg rpos rneg rclk2 tclk1 tser rser rclk1 fifo fifo 51.84 mhz div by empty write clock tser rser rclk2 cs62180b driver receiver cs61535a 6480 to 193 bit (or 256 bit) mapping circuit jitter attenuator figure a5. sonet application cs61535a 32 ds40f2
locked vt operation, table a1 shows potential sub-multiple data rates, and the impact on those rates on the maximum gap in the output clock of the fifo, and depth of fifo required. fifo depth will have to be increased for floating vt operation, with 8 bits of fifo depth being added for each pointer alignment change that can occur. the objective that should be met in picking a fifo depth and clock divider is keep the maxi- mum gap on the output of the fifo at 12 bits or less. twelve bits is the maximum jitter which can be input to the cs61535as jitter attenuator with- out causing the overflow/undeflow protection circuit to operate. the cs61535a then removes the remaining jitter from the signal. the receive path also requires a bit mapping (from 193 or 256 bits to 6480 bits). this mapping requires an input buffer with the same depth as use on the transmit path. this buffer also absorbs the output jitter generated by the cs61535as digital clock recovery. transformers recommended transmitter and receiver trans- former specifications for the cs61535a are shown in table a2. the transformers in table a3 have been tested and recommended for use with the cs61535a. refer to the "telecom trans- former selection guide" for detailed schematics which show how to connect the line interface ic with a particular transformer. in applications with the cs61535a where it is ad- vantageous to use a single transmitter transformer for both 75 w and 120 w e1 applications, a 1:1.26 transforer may be used. although transmitter re- turn loss will be reduced for 75 w applications, the pulse amplitude will be correct across a 75 w load. target rate (mhz) clock divider resultant rate (mhz) maximum gap fifo depth required ( m s) bits 1.544 32 1.620 6.2 10 21 1.544 33 1.571 3.9 6 26 2.048 25 2.074 3.4 7 34 table a1. locked vt fifo analysis parameter cs61535a receiver cs61535a transmitter turns ratio 1:2 ct 5% 1:1 1.5 % for 75 w e1 1:1.15 5 % for 100 w t1 1:1.26 1.5 % for 120 w e1 primary inductance 600 m h min. @ 772 khz 1.5 mh min. @ 772 khz primary leakage inductance 1.3 m h max. @ 772 khz 0.3 m h max. @ 772 khz secondary leakage inductance 0.4 m h max. @ 772 khz 0.4 m h max. @ 772 khz interwinding capacitance 23 pf max. 18 pf max. et-constant 16 v- m s min. for t1 12 v- m s min. for e1 16 v- m s min. for t1 12 v- m s min. for e1 table a2. transformer specifications cs61535a ds40f2 33
application turns ratio(s) manufacturer part number package type rx: t1 & e1 1:2ct pulse engineering pe-65351 1.5 kv through-hole, single schott 67129300 bel fuse 0553-0013-hc tx: t1 1:1.15 pulse engineering pe-65388 1.5 kv through-hole, single schott 67129310 bel fuse 0553-0013-rc tx: e1 (75 & 120 w) 1:1.26 1:1 pulse engineering pe-65389 1.5 kv through-hole, single schott 67129320 bel fuse 0553-0013-sc rx &tx: t1 1:2ct 1:1.15 pulse engineering pe-65565 1.5 kv through-hole, dual bel fuse 0553-0013-7j rx &tx: e1 (75 & 120 w) 1:2ct 1:1.26 1:1 pulse engineering pe-65566 1.5 kv through-hole, dual bel fuse 0553-0013-8j rx &tx: t1 1:2ct 1:1.15 pulse engineering pe-65765 1.5 kvsurface-mount, dual bel fuse s553-0013-06 rx &tx: e1 (75 & 120 w) 1:2ct 1:1.26 1:1 pulse engineering pe-65766 1.5 kv surface-mount, dual bel fuse s553-0013-07 rx : t1 & e1 1:2ct pulse engineering pe-65835 3 kv through-hole, single en60950, en41003 approved tx: e1 (75 & 120 w ) 1:1.26 1:1 pulse engineering pe-65839 3 kv through-hole, single en60950, en41003 approved table a3. recommended transformers for the cs61535a cs61535a 34 ds40f2
features socketed line interface device all required components for complete line interface evaluation configuration by dip switch or serial interface led status indicators for alarm conditions support for host, hardware, and extended hardware modes general description the evaluation board includes a socketed line interface device and all support components necessary for evaluation. the board is powered by an external 5 volt supply. the board may be configured for 100 w twisted-pair t1, 75 w coax e1, or 120 w twisted-pair e1 operation. binding posts are provided for line connections. sev- eral bnc connectors are available to provide system clocks and data i/o. two led indicators monitor de- vice alarm conditions. the board supports all line interface operating modes. ordering information: cdb61534, cdb61535. cdb61535a, cdb6158, cdb6158a, cdb61574, cdb61574a, cdb61575, cdb61577, cdb61304a, cdb61305a sep 95 ds40db3 35 crystal semiconductor corporation p.o. box 17847, austin, tx 78760 (512) 445-7222 fax: (512) 445-7581 line interface evaluation board cdb61534, cdb61535, cdb61535a, cdb6158, cdb6158a, cdb61574, cdb61574a, cdb61575, cdb61577, cdb615304a, & cdb61305a aclki tclk tpos (tdata) tneg rneg (bpv) rpos (rdata) rclk cs61534, cs61535, cs61535a, cs6158, cs6158a, cs61574, cs61574a, cs61575, cs61577, cs61304a or cs61305a reset circuit mode select circuit (tcode) +5v 0v led status indicators hardware control circuit serial interface control circuit ttip tring rtip rring xtl
power supply as shown on the evaluation board schematic in figure 1, power is supplied to the evaluation board from an external +5 volt supply connected to the two binding posts labeled +5v and gnd. transient suppressor d10 protects the compo- nents on the board from over-voltage damage and reversed supply connections. the recommended power supply decoupling is provided by c1, c2 and c3. ceramic capacitor c1 and electrolytic ca- pacitor c2 are used to decouple rv+ to rgnd. capacitor c3 decouples tv+ to tgnd. the tv+ and rv+ power supply traces are connected at the device socket u1. a ground plane on the compo- nent side of the evaluation board insures optimum performance. board configuration pins on line interface device u1 with more than one pin name have different functions depending on the operating mode selected. pin names not enclosed in parenthesis or square brackets de- scribe the hardware mode pin function. pin names enclosed in parenthesis describe the ex- tended hardware mode pin function. pin names enclosed in square brackets describe the host mode pin function. table 1 explains how to configure the evaluation board jumpers depending on the device installed and the desired operating mode. mode selection is accomplished with slide switch sw1 and jump- ers jp2, jp6, and jp7. the cs61535a, cs61574a, cs61575, cs61577, cs61304a, and cs61305a support the hardware, extended hardware, and host operating modes. the cs61534, cs61535, and cs61574 support the hardware and host operating modes. the cs6158 and cs6158a only support the hardware operating mode. hardware mode in the hardware operating mode, the line inter- face is configured using dip switch s2. the digi- tal control inputs to the device selected by s2 in- clude: transmit all ones (taos), local loopback (lloop), remote loopback (rloop), and trans- mit line length selection (len2,len1,len0). closing a dip switch on s2 towards the label sets the device control pin of the same name to logic 1 (+5 volts). note that s2 switch positions tcode and rcode have no function in hardware mode. in addition, the host processor interface connector jp1 should not be used in the hardware mode. two led status indicators are provided in hard- ware mode. the led labeled dpm (ais) illumi- nates when the line interface asserts the driver jumper position function selected jp1 - connector for external processor in host operating mode. jp2, jp6, jp7 a-a extended hardware operating mode. b-b hardware or host operating modes. jp3 in hardware or extended hardware operating modes. out host operating mode. jp4 c-c connects the aclki bnc input to pin 1 of device. d-d grounds the aclki bnc input through 51 w resistor r1. jp5 e-e transmit line connection for all applications except those listed for "f-f" on the next line. f-f 75 w coax e1 applications using the schott 12932/12532 or pe-65389/65566 at transformer t1. jp8 in shorts resistor r2 for all applications except those listed for "out" on the next line. out inserts resistor r2 for 75 w coax e1 applications using the cs61534, 35, 58, 74, or 77. table 1. evaluation board jumper settings line interface evaluation board 36 ds40db3
r16 1k w 8 rclk 2 tclk 3 tpos (tdata) 6 rneg (bpv) pin 3 tclk rclk pin 6 4 tneg 7 rpos (rdata) 1 aclki pin 7 aclki r1 51.1 w pin 4 s2 r15 100 w rv+ rv+ q1 2n2222 r6 470 w led d3 rv+ q2 2n2222 r5 470 w led d2 jp1 d9 1n914 d8 r14 4.7k w sip rv+ los dpm (ais) mode r18 10k w r17 10k w 511 12 23 24 25 26 27 28 len1/sdi len2/sd0 lloop/sclk taos/clke tcode rloop/cs sdi sdo sclk int cs len0/int s1 reset mode sw1 r4 221k w a a bb dd c c jp4 jp2 rcode c4 0.047 m f 3 6 875124 host:3-1,6-8 ext hw: 3-2, 6-7 hw: 3-4, 6-5 18 tring ttip 0.47 m f c5 tring ttip +5v 22 14 15 rv+ tv+ tgnd rgnd d10 p6ke 21 t1 (see table 2) 17 c2 0.1 m f c1 68 m f 19 rtip rring rring rtip 20 jp8 r2 4.4 w c3 1 m f rv+ rclk tclk rneg (bpv) aclki len1 [sdi] len2 [sd0] lloop [sclk] taos [ckle] xtalin {cs6158/58a: rt} xtalout {cs6158/58a: nc} los dpm (ais) mode 13 16 aa aa b b bb rtip rring tring pin 17 pin 18 9 10 ttip rv+ r13 (only included for cs6158/58a) 1k w (used only for e1 75 w applications with the cs61534, cs61535, cs6158, cs61574, or cs61577) cs61534, cs61535, cs61535a, cs6158, cs6158a, cs61574, cs61574a, cs61575, cs61577, cs61304a, or cs61305a u1: f f e e prototyping area rv+ len0 [int] rloop [cs] mring (pcs) rpos (rdata) tpos (tdata) mtip (rcode) jp6 jp7 jp5 e1: cxt8192 t1: cxt6176 (not included for cs6158/58a) + tneg (tcode) u1 r9 200 w r10 200 w t2 (see table 2) 2:1 gnd (0v) change r9 and r10 for e1 operation figure 1. evaluation board schematic line interface evaluation board ds40db3 37
performance monitor alarm. the led labeled los illuminates when the line interface receiver has detected a loss of signal. extended hardware mode in the extended hardware operating mode, the line interface is configured using dip switch s2. the digital control inputs to the device selected by s2 include: transmit all ones (taos), local loopback (lloop), remote loopback (rloop), transmit line length selection (len2, len1, len0), transmit line code ( tcode), and receive line code ( rcode). closing a dip switch (mov- ing it towards the s2 label) sets the device control pin of the same name to logic 1 (+5 volts). note that the tcode and rcode options are active low and are enabled when the switch is moved away from the s2 label. the parallel chip select input pcs is tied to ground in extended hard- ware mode to enable the device to be reconfig- ured when s2 is changed. in addition, the host processor interface connector jp1 should not be used in extended hardware mode. two led status indicators are provided in ex- tended hardware mode. the led labeled dpm (ais) illuminates when the line interface detects the receive blue alarm (ais). the led labeled los illuminates when the line interface receiver has detected a loss of signal. host mode in the host operating mode, the line interface is configured using a host processor connected to the serial interface port jp1. the s2 switch posi- tion labeled clke selects the active edge of sclk and rclk. closing the clke switch se- lects rpos and rneg to be valid on the falling edge of rclk and sdo to be valid on the rising edge of sclk as required by the cs2180b t1 framer. all other dip switch positions on s2 should be open (logic 0) to prevent shorting of the serial in- terface signals. resistor r15 is a current limiting resistor that prevents the serial interface signals from being shorted directly to the +5 volt supply if any s2 switch, other than clke, is closed. jumper jp3 should be out so the int pin may be externally pulled-up at the host processor inter- rupt pin. two led status indicators are provided in host mode. the led labeled dpm (ais) illuminates when the line interface asserts the driver per- formance monitor alarm. the led labeled los illuminates when the line interface receiver has detected a loss of signal. manual reset a manual reset circuit is provided that can be used in hardware and extended hardware modes. the reset circuit consists of s1, r4, r16, c4, d8, and d9. pressing switch s1 forces both lloop and rloop to a logic 1 and causes a reset. a reset is only necessary for the cs61534 device to calibrate the center frequency of the re- ceiver clock recovery circuit. all other line inter- face units use a continuously calibrated clock re- covery circuit that eliminates the reset require- ment. transmit circuit the transmit clock and data signals are supplied on bnc inputs labeled tclk, tpos(tdata), and tneg. in the hardware and host operating modes, data is supplied on the tpos(tdata) and tneg connectors in dual nrz format. in the extended hardware operating mode, data is sup- plied in nrz format on the tpos(tdata) con- nector and tneg is not used. the transmitter output is transformer coupled to the line through a transformer denoted as t1 in figure 1. the signal is available at the ttip and tring binding posts. capacitor c5 is the recom- mended 0.47 m f dc blocking capacitor. line interface evaluation board 38 ds40db3
the evaluation board supports 100 w twisted-pair t1, 75 w coax e1, and 120 w twisted-pair e1 op- eration. the cdb61534, cdb61535, cdb6158, cdb61574, and cdb61577 are supplied from the factory with a 1:2 transmit transformer that may be used for all t1 and e1 applications. the cdb61535a, cdb6158a, cdb61574a, cdb61575, cdb61304a, and cdb61305a are supplied with a 1:1.15 transmit transformer in- stalled for t1 applications. an additional 1:1:1.26 transformer for e1 applications is provided with the board. this transformer requires jp5 to be jumpered across f-f for 75 w coax e1 applica- tions. the cdb61534, cdb61535, cdb6158, cdb61574, and cdb61577 require the jp8 jumper to be out for 75 w coax e1 applications. this inserts resistor r2 to reduce the transmit pulse amplitude and meet the 2.37 v nominal pulse amplitude requirement in ccitt g.703. in addition, r2 increases the equivalent load imped- ance across ttip and tring. receive circuit the receive line interface signal is input at the rtip and rring binding posts. the receive sig- nal is transformer coupled to the line interface de- vice through a center-tapped 1:2 transformer. the transformer produces ground referenced pulses of equal amplitude and opposite polarity on rtip and rring. the receive line interface is terminated by resis- tors r9 and r10. the evaluation boards are sup- plied from the factory with 200 w resistors for ter- minating 100 w t1 twisted-pair lines. resistors r9 and r10 should be replaced with 240 w resis- tors for terminating 120 w e1 twisted-pair lines or 150 w resistors for terminating 75 w e1 coaxial lines. two 243 w resistors and two 150 w resistors are included with the evaluation board for this purpose. the recovered clock and data signals are avail- able on bnc outputs labeled rclk, rpos(rdata), and rneg(bpv). in the hard- ware and host operating modes, data is output on the rpos(rdata) and rneg(bpv) connectors in dual nrz format. in the extended hardware operating mode, data is output in nrz format on the rpos(rdata) connector and bipolar viola- tions are reported on the rneg(bpv) connector. quartz crystal a quartz crystal must be installed in socket y1 for all devices except the cs6158 and cs6158a. a crystal semiconductor cxt6176 crystal is rec- ommended for t1 operation and a cxt8192 is recommended for e1 operation. the evaluation board has a cxt6176 installed at the factory and a cxt8192 is also provided with the board. the cdb6158 and cdb6158a have resistor r13 installed instead of a crystal. this connects the rt pin of the device to the +5 volt supply. alternate clock input the aclki bnc input provides the alternate clock reference for the line interface device (aclk for the cs61534) when jp4 is jumpered across c-c. this clock is required for the cs61534, cs61535, cs6158, and cs6158a op- eration but is optional for all other line interface devices. if aclki is provided, it may be desir- able to connect both c-c and d-d positions on jp4 to terminate the external clock source provid- ing aclki with the 51 w resistor r1. if aclki is optional and not used, connector jp4 should be jumpered across d-d to ground pin 1 of the de- vice through resistor r1. transformer selection to permit the evaluation of other transformers, table 2 lists the transformer and line interface de- vice combinations that can be used in t1 and e1 line interface evaluation board ds40db3 39
applications. a letter at the intersection of a row and column in table 2 indicates that the selected transformer is supported for use with the device. the transformer is installed in the evaluation board with pin 1 positioned to match the letter illustrated on the drawing in table 2. for exam- ple, the pulse engineering pe-65388 transformer may be used with the transmitter of the cs61575 device for 100 w t1 applications only (as indi- cated by note 3) when installed in transformer socket t1 with pin 1 at position d (upper right). prototyping area a prototyping area with power supply and ground connections is provided on the evaluation board. this area can be used to develop and test a vari- ety of additional circuits like a data pattern gener- ator, cs2180b framer, system synchronizer pll, or specialized interface logic. evaluation hints 1. properly terminate ttip/tring when evaluat- ing the transmit output signal. for more informa- tion concerning pulse shape evaluation, refer to the crystal application note entitled "measure- ment and evaluation of pulse shapes in t1/e1 transmission systems." 2. change the receiver terminating resistors r9 and r10 when evaluating e1 applications. resis- tors r9 and r10 should be replaced with 240 w resistors for terminating 120 w e1 twisted-pair lines or 150 w resistors for terminating 75 w e1 coaxial lines. two 243 w resistors and two 150 w resistors are included with the evaluation board for this purpose. 3. closing a dip switch on s2 towards the label sets the device control pin of the same name to logic 1 (+5 volts). 4. to avoid damage to the external host controller connected to jp1, all s2 switch positions (except clke) should be open. in the host operating mode, the clke switch selects the active edge of sclk and rclk. line interface evaluation board 40 ds40db3
notes: 1. a letter at the intersection of a row and column in table 2 indicates that the selected transformer is supported for use with the device. the transformer is installed in the evaluation board with pin 1 po- sitioned to match the letter illustrated in the drawing to the left. 2. the receive transformer (rx) is soldered at location t2 on the evaluation board and is used for all applications. the transmit transformer (tx) is socketed at location t1 on the evaluation board and may be changed according to the application. 3. for use in 100 w t1 twisted-pair applications only. 4. for use in 75 w and 120 w e1 applications only. place jumper jp5 in position f-f for 75 w e1 applications requiring a 1:1 turns ratio. 5. transmitter return loss improves when using a 1:2 turns ratio trans- former with the appropriate transmit resistors. table 2. transformer applications transformer (turns ratio) 1,2 line interface unit 34 35 35a 58 58a 74,77 74a 75 304a, 305a rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx rx tx pe-65351 (1:2ct) a d a d a a d a a d a a a schott 12930 (1:2ct) b c b c b b c b b c b b b pe-65388 (1:1.15) d 3 d 3 d 3 d 3 d 3,5 schott 12931 (1:1.15) c 3 c 3 c 3 c 3 c 3,5 pe-65389 (1:1:1.26) d 4 d 4 d 4 d 4 d 4,5 schott 12932 (1:1:1.26) c 4 c 4 c 4 c 4 c 4,5 pe-64951 (dual 1:2ct) e e e e schott 11509 (dual 1:2ct) e e e e pe-65565 (dual 1:1.15 & 1:2ct) e 3 e 3 e 3 e 3 e 3,5 schott 12531 (dual 1:1.15 & 1:2ct) e 3 e 3 e 3 e 3 e 3,5 pe-65566 (dual 1:1:1.26 & 1:2ct) e 4 e 4 e 4 e 4 e 4,5 schott 12532 (dual 1:1:1.26 & 1:2ct) e 4 e 4 e 4 e 4 e 4,5 e t2 t1 d a c b t2 t1 line interface evaluation board ds40db3 41
figure 2. silk screen layer (not to scale) line interface evaluation board 42 ds40db3
figure 3. top ground plane layer (not to scale) line interface evaluation board ds40db3 43
figure 4. bottom trace layer (not to scale) line interface evaluation board 44 ds40db3
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